1. Field of the Invention
The present invention generally relates to fault detection methods, test circuits and semiconductor devices, and more particularly to a fault detection method for detecting a fault in a circuit that has a delay chain, a test circuit using such a fault detection method, and a semiconductor device having such a test circuit.
2. Description of the Related Art
Semiconductor devices having a delay chain made up of a plurality of delay cells are known. One example of the semiconductor circuit having the delay chain is a delay locked loop (DLL) circuit which controls and adjusts a time difference between an external clock and an internal clock by circuitry, so as to realize a high-speed clock access (or short clock access time) and a high operation frequency. In such a semiconductor circuit, if a certain delay cell fails, the delay chain cannot generate the correct delay, and the circuit cannot carry out the correct operation. Hence, when forwarding the semiconductor device (or semiconductor chip) having the semiconductor circuit from a factory, a test is carried out by inputting a test pattern from a tester to the delay chain, and judging whether or not a fault exists in the delay cell by the tester based on an output of the semiconductor device.
As the operation speed of the semiconductor circuit becomes higher, the pulse width of the signals input to and output from the delay chain becomes extremely narrow, and the signal frequency input to and output from the delay chain becomes extremely high. However, according to the existing technology, in order to enable the test to be carried out by an external tester by outputting an undistorted signal waveform from the semiconductor device, the pulse width must be approximately 4 ns or wider and the signal frequency must be approximately 250 MHz or lower. If the pulse width is less than approximately 4 ns or, if the signal frequency exceeds 250. MHz, the signal waveform is distorted when the signal waveform is output from the semiconductor device to the external tester, due to the capacitance of terminals (or pins) or an output load of the semiconductor device. Accordingly, there was a problem in that it is impossible to accurately detect the fault of the delay chain when the pulse width of the signal input to or output from the delay chain is extremely narrow or the signal frequency input to or output from the delay chain is extremely high.